The present invention is related to the field of solid-state electronic circuits, and more particularly to the field of digital-to-analog converters employing randomized dynamic element matching techniques.
Digital-to-analog converters (DACs) operate to convert signals representing values in the digital domain to the same values represented in the analog domain, and are therefore ideally linear devices. However, the non-ideal circuit behavior of practical DACs introduces non-linearities that cause harmonic distortion and limit the achievable spurious-free dynamic range (SFDR).
The continued growth in wireless technology has spawned an increased demand for large-scale integration digital-to-analog conversion techniques. For example, a technique frequently used in wireless communication products is direct digital synthesis (DDS). In DDS, analog signals, such as carrier tones, are synthesized using mostly digital circuitry. The front-end digital-to-analog converter (DAC) used to convert the input digital signal into an analog waveform limits the efficiency in many DDS systems. In particular, the production of harmonic distortion during the conversion places an upper boundary on the SFDR of the entire system.
In order to attenuate or eliminate harmonic distortion resulting from non-ideal circuit behavior in various multi-bit DACs, dynamic element matching (DEM) techniques have been successfully applied. Rather than using special fabrication processes or laser trimmed components to improve performance, non-ideal circuit behavior is accepted as inevitable, and signal-processing techniques are applied to mitigate the negative effects on DAC linearity.
An example of a popular multi-bit DAC architecture involves the use of a plurality of nominally identical current sources whose outputs are summed to yield a composite DAC. During monolithic integration of high-accuracy current sources for volume production of solid-state circuits, however, the problem arises that, due to current source manufacturing variations, individual current sources vary in the current they deliver. These current source manufacturing variations can largely be compensated for by the use of a current divider and by switching the currents of a plurality of current sources to three current paths in a xe2x80x9crotatingxe2x80x9d manner by means of a cyclic shift register, with the first and second current paths being fed half the current of the third path. By cascading a plurality of such current dividers, a high-accuracy monolithic integrated DAC can be implemented. The binary signal is caused to xe2x80x9crotatexe2x80x9d by means of a cyclic shift register, and the xe2x80x9crotatingxe2x80x9d signal drives a set of switches to turn the individual current sources on or off In order to utilize this xe2x80x9crotationxe2x80x9d method, the frequency of the shift signal for the shift register must be at least (2nxe2x88x921) times higher than the frequency of the sampling signal at whose pulse repetition rate the binary signals occur. However, use of such a shift signal is not always feasible, e.g. an oscillator operational at a correspondingly stable frequency is too expensive for a specific application. In addition, the frequency of the shift signal often lies in ranges that necessitate particularly careful design of, and specific manufacturing processes for, the integrated circuit.
Another approach applied in monolithic integration involves the input signal being applied to a conventional DAC, and first. processed so that its value is uncorrelated with that of the unprocessed input signal. Adding a digital random number to the input digital signal can effect this processing. The digital random number is then converted into analog form by a second DAC. An analog subtraction circuit then subtracts the analog version of the processed sum. The difference is the analog counterpart to the original digital input signal.
The present invention proposes the use of a new DEM technique suitable for applications requiring low-distortion DACs, such as DDS. It is demonstrated that harmonic distortion is eliminated, i.e., the DAC noise is white, and thus an optimal SFDR is achieved. These results are achieved by utilizing a topology that incorporates a bank of, preferably 1-bit, DACs, the outputs of which are summed together to yield a single multi-bit DAC. The DAC noise arising from mismatches between the individual 1-bit DACs is xe2x80x9cscrambledxe2x80x9d by randomly selecting one of the appropriate codes for each digital input value. A digital encoder is exploited to carry out the scrambling process, the ultimate effect being modulation of the DAC noise without modulation of the signal component of the DAC output.
A digital-to-analog converter used in converting digital input signals to analog output signals using a bank of, preferably 1-bit, DACs, or xe2x80x9cunit DAC elementsxe2x80x9d (UDEs) as follows. A multi-bit digital signal is received by an encoder, which translates the received signal into multiple one-bit binary signals. Each binary signal is received by a UDE that converts the binary signal to analog. The encoder implements a randomization algorithm that identifies the UDEs to be selected during each conversion cycle. The UDE analog output paths are connected through a summing node to generate the final analog output corresponding to the original digital input signal.